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Industry News 2008 P10
EV Group Expands Presence in Korea
(May 14, 2008) St. Florian, AUSTRIA — EV Group, equipment manufacturer for semiconductor, MEMS, and nanotechnology applications, announced the opening of a subsidiary, EV Group Korea Ltd., in Seoul, Korea to serve as a direct-to-customer site for sales, service, and support efforts for EVG's existing and potential new customer base. The subsidiary will reportedly house sales, service, process/application and administrative capabilities.
Vietnam - Chipscale Advanced Packaging Services Receives Certification
(May 14, 2008) Hanoi, VIETNAM — Vietnam-Chipscale Advanced Packaging Services, an outsource semiconductor assembly and test services provider based in Vietnam, has been presented with its investment certificate from th Vietnamese government, recognizing the company as a 100% foreign owned venture.
STATS ChipPAC Completes Qualification of Fan-in PoP
(May 13, 2008) SINGAPORE — STATS ChipPAC Ltd. announced the completion of full internal qualification of its Fan-in Package-on-Package (FiPoP) technology. Fully functional electrical samples are available, and production volumes are expected to ramp by the end of 2008.
Premier Semiconductor Opens Facility in Florida
(May 13, 2008) Tempe AZ — Premier Semiconductor Services, LLC announced the opening of a facility in St. Petersburg, Fl to provide quick-turn services for strategic east-coast accounts and to solidify Premier's growing counterfeit detection programs. Premier will reportedly offer a variety of counterfeit detection services such as functional electrical testing, decapsulation, XRF testing, solderability, and advanced visual inspection.
Avago Technologies Introduces RF Packaging Chip-scale Technology
(May 12, 2008) San Jose, CA — Avago Technologies, supplier of analog interface components for communications, industrial, and consumer applications; announced what it believes to be a breakthrough in packaging technology that it says will provide a new level of design flexibility. Called WaferCap CSP, it is reportedly the industry's first semiconductor-based chip scale packaging (CSP) technology.
Renesas Adopts Cadence Tool for Large Scale SoC and Flip Chip Design
(May 12, 2008) San Jose, CA — Cadence Design Systems, Inc. announced that Renesas Technology Corp. has successfully taped out its most advanced and large-scale system-on-chip (SoC) design to date using the Cadence SoC Encounter system. Hisaharu Miwa, general manager, Design Technology Division LSI Product Technology Unit at Renesas credits the system's memory capacity and fast turnaround time as the reason for the successful tape out.
Mentor Graphics Addresses IC Implementation Challenges
(May 9, 2008) Wilsonville OR — Mentor Graphics Corp. has aligned its integrated circuit (IC) implementation product lines under the design-to-silicon division to better address the design and manufacturing challenges of 45nm and smaller process nodes.
Endicott Interconnect Awarded Defense Contract Modification
(May 9, 2008) Endicott, NY — The U.S. Department of Defense has awarded Endicott Interconnect Technologies, Inc.(EI) a $148.6M contract modification for the continuation of the current program to produce card frame assemblies including HyperBGA organic semiconductor packaging, multi-chip module assemblies, printed circuit boards, functionally-tested circuit board assemblies and engineering services in support of a high reliability, high performance computing application.
SMTA's 3D/SiP Symposium Promotes Industry-wide Collaboration
Last week's 3D/SiP Symposium hosted by SMTA, and co-sponsored by Advanced Packaging magazine, turned out to be an intimate gathering of approximately 55 attendees representing not only the U.S., but Canada, France, Japan, Taiwan, United Kingdom, Austria and the Republic of Korea.
IEEE International Interconnect Technology Conference Goes 3D
(May 7, 2008) Burlingame, CA — When the IEEE International Interconnect Technology Conference convenes at the Hyatt Regency San Francisco Airport Hotel, Burlingame, CA, June 1-4, the focus will be squarely on 3D technologies. Attendees will have the opportunity to gain both fundamental knowledge and practical manufacturing advice from 3D experts at chip companies and universities from around the world.
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