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By Françoise von Trapp, managing editor
It's common knowledge that Moore's Law, as we know it, has reached a point where it can no longer follow its normal progression of doubling the number of transistors on a chip each year. In his keynote address at IMAPS International, John Volper, V.P corporate R&D, Raytheon, suggested that the key to breaking through CMOS scaling roadblocks may lie with in the development of photonic devices.
They way Volper explains it, circuit performance has historically increased at a rate of 74% per year, but began to diverge from that pace around 2000. At this time, Volper says intrinsic device speed has been exploited at the circuit level, and is experiencing thermal limitations. "CMOS scaling is hitting a roadblock in heat dissipation," said Volper. "Because of this thermal limitation, we can't turn up frequency without dissipating more power." He said one solution was to turn to multicore processors, which spread out the heat and power.
Thanks to research funded by DARPA in 2007, Intel and IBM announced they had solved the gate leakage problem with a hafnium-based gate insulator and metal gate. But this only addressed stand-by power concerns. Other approaches looked at reducing voltage or using MEMS switches, putting an open circuit to isolate blocks of power. However, when interconnect limits are reached, what comes next?
Volper said that developments in 90nm feature sizes enable the opportunity of silicon nanophotonics, piggybacked on the CMOS infrastructure. Offering up the term application specific electronic and photonic integrated circuit (AS-EPIC), he explained this seamless integration of electrons and photons will allow functions to be combined, and that intra-chip photonic connectors enable the continuation of Moore's Law. By removing the interconnect bottleneck, functionality and capability can be extended. "It used to be (before these developments) that power was too high and devices were too big," noted Volper. "Now, those issues are off the table."
The next step is to enter the 3D integration race with photonic interconnects. To this end, Volper says DARPA has their own 3D IC program, which is divided into 3 parts; working with RTI with die-level stacked chips; IBM, MIT, and Ziptronix for wafer level approaches that focus on circuits first, followed by 3D integration; and finally monolithic 3D fabrication.
In summary, Volper noted that the time for exploiting device scaling to extend performance and functionality is over. Improvements will continue through a combination of device and interconnect architecture advancements throughout the supply chain.
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