Advanced Packaging - The Riley Report

The 3D Marathon Continues
by George A. Riley, Ph.D. contributing editor
3D packaging research papers drew crowds at the Advanced Technologies sessions of this month's IMAPS 2008 International Symposium. Five of the 12 papers directly addressed 3D topics; 4 of the 5 were from university research teams.

The industry 3D contributor, Endicott Interconnect, Inc., presented device-level fabrication, integration, and electrical performance of modified conductive adhesives for Z-axis high-density substrate and package interconnections. Adhesives tested included micro/ nano conductive particles, conductive polymers, and low melting-point alloys.

Adding nanoparticles to microparticle adhesives reduces the sintering temperature of the composite without affecting electrical conductivity. Adhesives doped with conductive polymers show volume resistivity similar to the micro-filled adhesives, but with considerably higher tensile strengths.

Z-axis interconnections for test assemblies required filling 5,000 to 200,000 board holes with selected conductive adhesives. Cores with no signal planes served as "joining cores" between two signal layers, completing electrical connections during board lamination. Conductive paste showed good signal transmission to 25GHz, suitable for complex high-performance multi-layer boards.

A new 3D approach, presented by Hongik University(Korea), is to replace the copper-filled silicon vias common to most 3D stacks with tin-filled vias. Copper requires a lengthy and complicated electrodeposition process to keep vias void-free. Also, the copper via-to-bump interface at the die surface is a potential mechanical weak spot.

Tin TSV formation begins conventionally with deep reactive ion etch (DRIE) to form vias, and seed layer sputtering before electroplating. The electroplated tin need not uniformly fill the vias; at reflow, the tin will fill any voids. CMP and backside grinding exposes via ends.

Vertical interconnections may be made either by interlocking joints or melted joints. Smaller diameter copper bumps plated underneath the vias are inserted into the lower die via openings on assembly. Alternatively, solder bumps electroplated underneath the vias form a reflowed connection upon chip stacking. Interlocking bumps showed 50-newton shear strengths; reflowed showed 30 – 40 Newton shear strength.

Tin via advantages over copper include a wider electroplating process window because vias need not be completely filled; shorter process times because tin electroplates faster than copper; faster CMP because tin is softer than copper; increased ruggedness from the interlocking joints and melt joints.

The University of Arkansas reported on a novel 3D packaging technology designed to handle high heat flux while providing high-speed interconnections. Copper filled TSV are formed in the usual manner to provide signal paths from active devices to the back side of individual layers.

Compliant copper posts and dams are plated on the back side of most layers, providing mechanical support while creating micro-fluidic channels for cooling. The 100µm-high posts and the dams are joined to matching pads on adjacent layers by copper/tin intermetallic.

The advantages of this structure include: removing heat from individual die layers; using known good die (KDG) to reduce yield loss; separating heterogeneous layers to minimize the effect of CTE mismatch; allowing power to be distributed independently to different layers.

A four-layer test vehicle is being completed, based upon a new method of adhesive wafer bonding. Thin-film copper resistors in each layer will simulate device heat dissipation. Resistive temperature sensors in every layer will monitor cooling performance. First experimental results will be used to verify the design.

Another paper from Hongik University (Korea) described filling copper TSVs without requiring lithography and CMP by using pulse-reverse plating with proper concentrations of various additives. Reversing polarity prevents copper buildup that would close the via opening prematurely. Efficient electropolishing replaces CMP.

Of course, many laboratory innovations never make it to the factory floor because of costs or other commercial considerations. Still, the continuing ferment of 3D research promises future improvements. Full details of these and 8 other advanced technology papers are available in the IMAPS symposium proceedings.

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