Advanced Packaging Online Article |  | |
(May 12, 2008) San Jose, CA — Cadence Design Systems, Inc. announced that Renesas Technology Corp. has successfully taped out its most advanced and large-scale system-on-chip (SoC) design to date using the Cadence SoC Encounter system. Hisaharu Miwa, general manager, Design Technology Division LSI Product Technology Unit at Renesas credits the system's memory capacity and fast turnaround time as the reason for the successful tape out.
"Given the complexity of this design and our aggressive schedule constraints, using a traditional ILM approach to hierarchical design was infeasible, and a new approach was required," explained Miwa, adding that SoC Encounter's hierarchical layout handling and 'dynamic' timing modeling technology coupled with its automatic floorplan synthesis and integrated flip-chip features allowed them to meet performance and schedule goals while reducing die-size and manufacturing costs.
"Renesas' experience and results with SoC Encounter, demonstrates their confidence in its ability to meet and exceed their requirements for advanced designs." said David Desharnais, group director of IC Digital product marketing at Cadence.
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