Advanced Packaging - Flip Chip Goes 3D

By Daniel F. Baldwin, Ph.D. and Paul Houston, ENGENT, Inc.
Current 3D packaging solutions involve a mix of high density circuit boards with stacked ICs using wire bond interconnect. With advances in wafer-thinning technology, 3D packaging now provides a robust platform for achieving high levels of integration, small package footprints, and thin package profiles. For emerging applications, further component miniaturization with the added benefit of 3D integration can be realized by face-to-face bonding of fine-pitch flip chip components and low-profile passives onto a redistribution layer (RDL) of another silicon component (a wafer level chip scale package – WLCSP). In this manner, a flip chip driver can be mounted directly onto a CSP memory component, ASIC, etc. A low cost, 3D WLCSP technology has been developed that leverages existing infrastructures of WLP and high-volume flip chip assembly.

This novel 3D-WLCSP package consists of a base wafer processed using conventional WLCSP techniques including an RDL and wafer-applied solder balls. The wafer-level RDL is designed such that a companion thinned die can be flip chip assembled directly onto the RDL between the WLCSP solder balls as shown in Figure 1. The package architecture consists of a base silicon wafer having I/O redistribution at the wafer level that includes flip chip interconnect pads for a mating die and solder balls for 2nd level interconnect. A thinned die is used to prevent 2nd level assembly interference. The thinned die is mounted onto the wafer using conventional flip chip techniques. Additionally, the base wafer can incorporate through silicon vias (TSVs) and one or both sides of the base wafer can include wafer-level redistribution technology. Figure 2 shows an example of a 3D-WLCSP partial wafer assembly. Both a conventional dispensed underfill material and process and a jetted underfill material and process (right) are shown.

During development of this technology, flip chip pitch and bump size varied 85 and 200 µm. The finer pitch flip chip designs were found to have slightly lower yields then larger pitch devices and yields were found to be sensitive to flux amount for the finer pitch assemblies and relatively insensitive for the larger pitch assemblies. High yields were achieved for the 200 and 95 µm pitch assemblies. Both positive displacement pump dispensing and jet dispensing were demonstrated for 3D-WLCSP processing. Tighter control of the underfill volume and a lesser degree of bleed-out onto the WLCSP solder balls was achieved with the jetted underfill technology.

Reliability results indicated that the underfill selection had a large impact on the reliability of the 3D-WLCSP. Flux selection had a lesser impact on reliability. Three of the capillary underfill and flux systems (of the 12 evaluated) showed robust LLTS reliability. The higher reliability capillary underfills tended to have higher modulus and lower CTEs relative to the lower reliability materials. Minimal delamination was observed in the flip chip assemblies throughout the LLTS and unbiased autoclave reliability tests for the three high performing material sets.

No flow underfills have also been demonstrated as potential solutions for the 3D-WLCSP assemblies. Yield results and reliability of the no flow underfill assemblies is closely tied to void formation during flip chip reflow. Minimizing void formation results in markedly improved yields and reliability.
It has been found that 3D-WLCSP packages can be fabricated with robust yields and high reliability. These innovative package structures leverage the well-known infrastructures of wafer level packaging, wafer thinning, and high speed flip chip assembly. Further functionality can be achieved when TSVs are added.

Daniel F. Baldwin, Ph.D. and Paul Houston may be contacted at ENGENT, Inc., 3140 Northwoods Parkway, Suite 300A Norcross GA 30071; www.engentaat.com.

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