|
by Françoise von Trapp, managing editor
Last week's 3D/SiP Symposium hosted by SMTA, and co-sponsored by Advanced Packaging magazine, turned out to be an intimate gathering of approximately 55 attendees representing not only the U.S., but Canada, France, Japan, Taiwan, United Kingdom, Austria and the Republic of Korea. The 3-day event kicked off with a half-day workshop led by Lee Smith of Amkor Technology that covered "3D Packaging Applications, Requirements, Infrastructure and Technologies," and featured keynote presentations by Dongkai Shangguan, VP and senior fellow from Flextronics, and Judy Priest, of Cisco Systems.
Shangguan addressed the challenges in 3D/SiP packaging and assembly, focusing on supply chain demands due to shorter product life cycles. He explained that historically, product life cycles allowed for the development and fine-tuning of new processes to occur consecutively through the supply chain, focusing on one stage at a time before considering the next. This has changed with the shortened life cycle. He called for collaboration among players in the supply chain to work together and develop solutions in parallel early in the lifecycle. "This is the only way to meet requirements of short product lifecycles demanded by customer and consumers," he said.
To illustrate his point, Shangguan addressed package-on-package (PoP) assembly. He said there are two options to consider, pre-stacking and in-line stacking, and in his opinion, pre-stacking is not a good solution to the industry. With in-line stacking, CSPs are supplied to the point of use – the SMT line. This allows for greater flexibility and scalability in supply chain management, enables configurable assemblies, and allows for better management of package test and yield issues, among other things.
He also touched on key challenges of SiP, citing a need for more complex test equipment; high dielectric materials and reworkable underfills; equipment that is modular and flexible, accurate, repeatable, and can handle 3D assembly; more advanced design and simulation tools; and yield manufacturing. These needs place demand on every segment of the supply chain, he noted. "There's a gap in capabilities and traditional process and newer technologies," he said. "We need to look at volume production solutions and figure out how to bring technology from R&D to high volume production."
Accordingly, during the duration of the symposium, speakers from across the supply chain shared recent developments in their specific sectors developed with 3D and SiP processes in mind. Day one centered on challenges involving stacked packages and SiP assembly, while Day 2 was dedicated to wafer-level technologies such as flip chip processes, TSVs and 3D Interconnects, thermal analysis and advanced substrate technology. Here's a sampling of what went on.
Gene Dunn, of Panasonic Factory Solutions of America presented a paper authored by his colleague, Joanne Wildheart, on PoP assembly using solder on pad (SoP) technology. Dunn said as we're seeing finer pitch and increased density due to multiple die in the bottom package, mold cap height is a critical factor. The SoP approach allowes you to keep mold height by adding solder balls to bottom package. The result is increased standoff with narrow pitch and more collapse than with the use of a large ball alone. The key to the success of this approach is the dipping material, explained Dunn. Although Panasonic is an equipment company, research engineers delved into materials development to create a PoP flux and paste developed specifically for SOP applications with higher viscosity and tackiness to reduce tendency to slop.
Mitch Holzer, of Cookson Electronics also addressed the flux and solder paste dilemma from a rheology and process parameter perspective. "It's important to have tight process control over solder paste/flux picked up by BGA ball," he explained. "There needs to be enough tack and shear resistance to hold ball in place." He added that because rework of PoP is complex, it's important to achieve high-yield first pass.
Other presentations addressing materials solutions included SunSoon Park, of Amkor's discussion of conformal coating technologies for EMI shielding of SiPs; the results of a flux asnd underfill compatibility study for flip chip interconnects, from Daniel Baldwin, Ph.D. of Engent, Inc. In a second presentation, Baldwin also addressed research being done at Georgia Tech's PRC on interfacial adhesion of nano-particle silver interconnects.
Addressing the challenge of inspecting PoP stacks was Janet Semmens, of Sonoscan, who explained how acoustic micro-imaging can be used to successfully detect voids and defects in die stacks. "As we go to different die-attach levels, we see different features, and can do level-specific imaging." She explained. "We can get an idea where problems are occurring in the process." As a byproduct of developing the process, have they been able to determine if certain die levels are most prone to defects? "They seem to occur randomly," she said. "People are surprised by that. More often find no defects, and that's a challenge when trying to prove that the technology works to find defects."
Also in the inspection category, William Baker, of Xradia, Inc, talked about the company's advancements in 3D package inspection using high resolution and contrast X-ray. He said that X-ray tomography technique has been used successfully to study TSVs and observe voids in detail because tomographic imaging and virtual slices show the shape of the void in 3D.
One of the most noteworthy presentations was from Phil Garrou, of Semprius, Inc. who explained the company's novel process of micro-transfer printing, which is essentially a massively parallel pick-and-place process. This process involves the formation of semiconductor chiplets on standard wafers in a fab environment. The oxide layer is etched out around and under each chiplet, leaving a thin tether to keep them attached. First, a transfer stamp is fabricated from a moldable silicone compound using a photo lithography process. Using the stamp, ever every fourth chip is picked off the source wafer and deposited on target substrate at whatever pitch is determined. The pressure of stamp fractures tethers and picks up the chips. This is what makes this fascinating, because seldom do you see a process in which the goal is to break the silicon. The stamp has natural tackiness to it. Each component is held on substrate using thin layer of adhesive. Garrou said that epitaxial lift-off (ELO) assembly methodology is key. The substrate has to be a little stickier than the stamp. No residue is left behind, but the completed device still goes through standard micoelectronic cleaning process.Garrou said Semprius is working with X-FAB to do chiplet fabrication. Currently, a hand-built tool designed by researchers at the University of Illiinois has been used to develop the process. The company is working to develop tool with vendor and hopes to put it into production by 2009. Targeted applications include PV modules, 3D heterogeneous integration such as broadband RF, and mixed circuit assembly.
Garrou was questioned about yield and placing known good die (KDG). He replied that since the wafer is inspected prior to placement, you know which die are bad. "It's still advantageous to replace bad die with good, and then move thousands at once." He explained.
Other presentations addressing assembly techniques to improve yield and speed up volume production included Gerald Steinwasser's discussion on advancements in flip chip die sorting, handling and inspection, and Ranga Ranganathan, of Linear Technology Corp's paper, µModule LGA Package and Assembly.
Also on hand to report on the progress of several consortiums were Paul Siblerud, Semitool who updated the group on EMC3D's holy grail of cost-effective TSVs; and Ritwik Chatterjee, Ph.D. of Georgia Tech, who talked about the global consortium on 3D all system silicon module (3DASSM), scheduled to launch in October.
It was great to connect with so many familiar people, and absorb their knowledge. Several of the technologies being discussed will be featured in upcoming issues of Advanced Packaging, and AP Semi-monthly. The venue alone — The Washington Duke Inn and Golf Club — made this a worthwhile experience. I expect that if it's repeated next year, attendance will increase. In any case, sign me up.
|
Web Exclusives 
Add RSS Feed
