Advanced Packaging - The 3DASSM Consortium: An Industry/Academia Collaboration

Ceramic substrates were the basis of high performance IC packages until 1990. Since then, for cost and performance reasons, organic substrates have taken over. However, organic substrates seem to have reached their limits in wiring density, cost, and thermo-mechanical performance such as warpage and thermal management. Recent advancements using Si wafer as the substrate with through-silicon via (TSV) replacing flip chip and wire bond, and with embedded thin-film components combined with its outstanding intrinsic thermal properties such as CTE and thermal conductivity, may allow for part or the entire system to be made of silicon. This is referred to as silicon package replacing organic package. Another concept to silicon systems calls for the seamless integration of IC with its front and back end, as well as thin-film fanout wiring typically done with organic packages. All these concepts may lead to an all silicon system for ICs, packages and boards. Silicon, however, presents several challenges to achieve this vision, such as its electrically conducting properties, high fabrication cost, and reduced mechanical strength.

The Packaging Research Center (PRC) at the Georgia Institute of Technology (Atlanta, GA), in partnership with Fraunhofer IZM (Berlin, Germany) and Korea Advanced Institute of Science and Technology(KAIST) (Daejeon, South Korea) will launch a global industry consortium titled 3D All Silicon System Module (3D-ASSM) in October, 2008. This consortium will explore and develop Si as the IC and system technology by assessing system-level benefits, identifying the challenges of Si based systems, and by executing focused, cross-disciplinary research to address the challenges and exploit the advantages of such systems. The objectives will include system miniaturization, component integration, superior electrical and thermal performance, greater reliability, hetero-integration of components, reduced form factor, and low-cost process innovations.

A three phase execution strategy is envisioned for this program. In the first phase, the focus will be on key building block technologies in five thrust areas: Electrical and thermal design and test; Multilayer Si substrate; Low cost TSV; Embedded thin-film actives and passives; and IC to Si package to board interconnections. Approximately 20 projects have been proposed across these five thrust areas. At the end of the first phase, some technologies from these thrust areas will be integrated to demonstrate an advanced Si package such as a BGA as shown in Figure 1. The next phase will continue to enhance the building block technologies that were executed in the first phase, including continuation of some projects or launching entirely new projects. The second phase will also deliver an integration which will be a more advanced and highly integrated Si module incorporating a majority of the various building block technologies developed in the first phase. Finally, the third and final phase will achieve a complete all Si system.

Prior to the launch of this global consortium, there will be four workshops held throughout the world to introduce the program to potential industrial partners. The first workshop was held on the campus of GeorgiaTech (Atlanta, GA) on March 11-12, 2008. There was a lot of interest with over 80 participants from 45 organizations attending this event. The workshop was highly interactive and useful in the shaping of the program. The general strategy of the program, as well as first-phase project details was shared during this first workshop. The next workshop will be held in May 5-6, 2008 in Berlin, Germany, where a revised set of projects and integration plans will be discussed. Subsequent workshops will be held in Japan on July 9, 2008 and Korea on July 11, 2008 prior to the launch of the consortium on October 1, 2008.

For more information on this consortium please contact Ritwik Chatterjee, Ph.D. email: ritwik@ece.gatech.edu; 404/385-7302

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