Advanced Packaging - From the Editor

(March 19, 2008) — Even with industry-wide slowed economic growth, these are exciting times for the assembly, test, and packaging sector. We've been hearing it over and over for the past few years; and I heard it again from two presenters in the space of an hour at the IMAPS Global Business Council held Monday, March 17, 2008, in Scottsdale, AZ. Packaging is key to solving semiconductor issues in this consumer-driven marketplace. 3D, wafer-level packaging (WLP), and system-in-package (SiP) have changed the semiconductor electronics manufacturing environment. The pace of change is accelerating, particularly in the packaging space.

"We are in a period of unprecedented change. Conventional professes can no longer meet roadmap requirements," noted Bill Bottoms, Ph.D., chairman and CEO of NanoNexus, Inc. in his keynote address. Bottoms offered a thorough examination of the technology challenges we face according to the ITRS roadmap, along with suggested solutions. It all comes down to several things: the incorporation of nanomaterials into packaging technologies that address thermal, electrical, and structural issues; novel device architectures; 3D integration to continue functional density; and SiP as the solution-of-choice for the majority of consumer products. Bottoms emphasized the importance of 3D integration throughout his talk, and even joked, "every time there's a conference on 3D, you can't get a hotel room. Everyone is working.on 3D integration."

I got the feeling that might be the case almost a year ago at SEMICON West 2007, and again at SEMICON Europa 2007, when all the buzz was about taking steps to commercialize through-silicon via technology both in the technical sessions, and on the exhibition floor. Paul Siblerud of Semitool commented recently that 3D integration is taking off quicker than he expected.

In this climate of accelerated change, with focus on packaging, Jim Walker, V.P. of research, Gartner Dataquest, and Advanced Packaging magazine advisory board member, addressed the packaging supply chain. "The semiconductor business model has to change, because of the consumer-driven market," he said. "There's too much to be done, too fast, at too low a cost to do it with the previous business model and be successful."

Last week, Gartner issued a press release that talked about the packaging sector's growth, as compared to the semiconductor industry as a whole. While its not exactly soaring, says Walker, it is experiencing double the growth of the rest of the industry.

This could be due to the fact that according to Walker, packaging sits right in the middle of the semiconductor supply chain, between wafer fab and final assembly. Traditionally, front-end fabs operate with a gross profit margin of 45%. Packaging firms realize a 20-30% margin, while EMS providers' have a 5-10% margin. What is happening, according to Walker, is that with wafer-level packaging (WLP), the packaging group is moving up the food chain into the fab's margin to get the value-add, and at the same time, with system-in-package (SiP) solutions, is taking the value-add from the PCB/manufacturing system. As a result, packaging is growing in both directions, capturing more value-add and realizing better margins. This may explain why the assembly, test, and packaging sector of the industry has been growing at twice the pace as the industry as a whole since 2001. Packaging technologies are in the position to solve issues, he says. We couldn't agree more. And that's why we've been focusing a lot lately on 3D integration and WLP technologies.

In this issue, read about Tessera's introduction of one of the industry's first TSV solutions, SHELLCASE MVP technology, announced yesterday at Image Sensors Europe in London. I had the opportunity to interview Shlomo Oren, GM of Tessera Israel, about this next-generation in the SHELLCASE image sensor packaging technology family. In addition, "Solder Ball Transfer for Flip Chip and WLCSPs", by Andrew Strandjord of Pactech, describes a novel ball placement process for wafer bumping both flip chip and wafer level chip scale packages (WLCSP).

And the Advanced Packaging Roadshow crew was on the move once again, this time reporting from Research Triangle Park, in Raleigh, NC, with a visit to Nextreme Thermal Solutions. We'd heard so much about their work with thermal copper pillar bump technology, that we wanted a first-hand look at their operation. We think they're on to something with this enabling cooling technology, as they address one of the ITRS roadmap challenges Bottoms discussed in his keynote.

My enthusiasm for 3D integration inspired Brigitte Wehrmann, marketing communications manager for SUSS MicroTec's lithography division, to crown me Queen of 3D, (Q3D for short). SUSS will sponsor the first in the next 3D webcast series April 30, which covers lithography applications for 3D packaging by looking at image sensor packaging, and 3D lens printing. Details of that event are forthcoming. In the mean time, I'll wear the Q3D tiara proudly, and look forward to the rest of this week in Scottsdale. I'm anxious to learn more about what we can expect to see not only in 3D, but in other areas covered by this symposium, including WLP and MEMS.

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