Advanced Packaging - 3D Packaging Processes

(March 5, 2008) — This article is the third in a series on 3D packaging technology, and summarizes information presented during a January 2008 webcast hosted by Advanced Packaging magazine. Participants were: Fred Roozeboom, Research Fellow, NXP Semiconductors and professor at TU Eindhoven; Kai Zoschke, Research Engineer for Fraunhofer IZM; and Thorsten Matthias, Director of Technology North America, EV Group.

The roadmap for 3D system-in-package (SiP) products has evolved from first-generation RF modules — based on a passive platform — to the next-generation versions. A turning point in the technology is anticipated for the third and fourth generations, where fine vias connect the die mounted either on top or below the passive platform die.

A via is a hole in a silicon wafer, which is insulated and filled with a diffusion barrier and/or a seed liner and a conductor fill, usually copper. Fine vias provide several functions: RF-signal transport, grounding, thermal heat dissipation, and redistribution of dissimilar pitch dimensions. For example, the active die could be a deep sub-micron die and the MEMS die normally has rough dimensions.

DRIE Etching
The first process of via drilling is DRIE. The Bosch process is the mainstay in commercial via etching, and involves a sequential alternative cycling of etch and passivation steps. During etch steps there is a bias voltage on the chuck supporting the wafer, which is used to induce an ion flux from the plasma above. These ions are then drawn towards the substrate, which is etched in an isotropic way. This step is interrupted by the passivation step with a fluorocarbon gas that polymerizes to form the (blue) layer on the wall and bottom. Bosch anisotropic etching is thus repeated in an ionic domain.

The etch rate is still a bottleneck in making this a commercial process. However, progess is being made. Researchers at the Technical University in Eindhoven, have demonstrated that etch rates can be increased by using more intense plasma sources such as expanding thermal plasma. Bosch claims that within a few years they, in cooperation with DRIE tool vendors, will have the means to etch much faster (e.g., 100 µm/min). The improvements include faster gas switching rates and shorter passivation, as well as etch gases under higher pressure.

DRIE etching is fundamentally constrained by Knudsen transport limitation — limited diffusion of the etching species into features with limited dimensions. Transport probability decreases for smaller feature dimensions, as well as for larger aspect ratios, i.e. thicker wafers — the thicker the wafer, the higher the etch time needed. One variable is to use thinner wafers which reduces etch time, but then thin-wafer handling issues may be introduced.

DRIE Etching of Cylindrical and Tapered Vias
DRIE etching of tapered structures can facilitate via filling, and eliminates the need for a pure Bosch process. If both etching and passivation gas is administered in a delicate balance through a continuous process to fix the passivation on the sidewall, the resulting via will be tapered. This enables easier physical vapor deposition (PVD) of seeding and subsequent electroplating.

Copper Seeding and Plating
The use of insulating layers is fairly general. Layers, such as silicon oxide or nitride, can be easily adapted from regular CMOS technology. The diffusion barrier, seed liner, and subsequent conductor fill is a little bit more complex.

Two main methods are used for making vias. The first starts with a blind via with a seed in it, and continues with electroplating. The second method starts with a thin wafer with the thru-hole via already etched, followed by "bottom-up plating" by first applying a dry layer by PVD, or other methods. Bottom-up plating does not require a seed layer.

An elaborate seed method uses low-pressure metal organic chemical vapor deposition (MOCVD), using a copper metal organic vapor. The seed layer was then reinforced by subsequent plating. Thus achieving complete filling for aspect ratios above 10:1. However, adhesion can be a concern with CVD copper seeding. Generally, copper adheres better when it has been deposited by PVD.

Bottom-up plating begins with the creation of a blind via whereby isolation is applied. Next, a sacrificial PMMA layer — applied by spin coating — polymerizes and forms a Roman bridge that can be planarized by CMP. Next, a dry seed layer is applied by PVD. The wafer is thinned from the back to open up the via. Annealing at 300°C allows the PMMA bridge to be removed, leaving a completed seed layer ready for Cu bottom-up growth.

Within the EMC3D consortium, Semitool and others provides electroless liner deposition. Electroless deposition can deposit layer (barriers and seeds) in a non-seeded open via. Subsequent Cu-electroplating will result in full-via height conformal filling; unlike PVD seed layers followed by electroplating, which fail to fully fill a 50-µm diameter.

Paste printing is a low-cost alternative to via filling, especially for less stringent applications requiring less conductive copper. In this method, the filling is done by so-called doctor blades that rub Cu-paste back and forth over the wafer surface into the vias, comparable to filling a drilled hole with putty in a wall. In co-operation with Sanyu Rec (Japan), their vacuum filling equipment was applied.

NXP, in cooperation with other organizations, continues to explore and develop cost-effective alternatives in copper via filling.

3D system integration is a key technology driven by application areas requiring ultra-compact smart systems such as image sensors, ultra-small sensor nodes, high memory density and capacity, parallel processor architectures etc. Advantages for 3D system integration include: reduction of system volume, weight and footprint; improvement of integration density and signal transmission speed as well as reduced power consumption; And the potential for high volume low cost production. Additionally, 3D system integration provides the only path for heterogeneous integration of components from different technologies e.g. MEMS, processor, memory etc.

The primary 3D integration approach Fraunhofer IZM is exploring is vertical system integration, which is based on stacking tested front-end devices with high-aspect ratio TSVs at wafer level. Another approach is the fabrication of silicon interposers with tapered or straight vias, which carry the system components. These interposers can either be completely passive or can carry integrated passive components as well. A third, modified approach deals with embedding thinned circuits into the dielectric layer on top of a device wafer or silicon interposer with additional integrated passives. These configurations can be also stacked using TSV and micro solder bumps.

Technological requirements for 3D system integration include robust and precise thinning, a handling concept for thin silicon wafers, and through-silicon via (TSV) formation processes like deep via etching, deep via dielectric isolation and deep via metal filling. Lastly, bonding and wafer-level assembly processes are required.

The core processes for all wafer level stacking approaches are TSV fabrication, and the handling and assembly of thinned devices (Figure 1). Assembly for can be accomplished with either wafer-to-wafer or chip-to-wafer bonding. The wafer-to-wafer approach has yield challenges if, for example, a bad die from one wafer is bonded to a good die on the other. This approach will also not work if the two chip types on both wafers have different size or step-and-repeat values. As a result, Fraunhofer is focusing on chip-to-wafer assembly, which can be done chip-by-chip or in parallel by bonding all chips in one step using a temporary carrier where the devices are transferred before.

For the thin-wafer handling, Fraunhofer IZM supports two major concepts. The first is temporary bonding using polyimide, BCB, or epoxy on handling wafers, which allows higher backside processing temperatures. The downside is that these materials are hard to remove. The second involves using thermoplastics for bonding, which allow low backside processing temperatures and are more easily removed. Another concept is the use of electrostatic chuck for clamping thin wafers. This involves using wafers with electrode structures on which thin wafers can be placed. By charging the electrode structure within the carrier wafer, an electrostatic force is established which bonds the thin wafer on top of the carrier wafer. In the case of a silicon-based chuck, you can profit from the well-known mechanics parameters of silicon, and can be fully compatible to front-end equipment and technology. Also, it features up to 16-hour chucking time and enables backside processing of thin wafers, such as plasma-enhanced CVD (PECVD), as well as wet processing.

Vias are etched into a completely processed device wafer after backside processing. Then, the vias are filled, fabricating the necessary interconnection layers (e.g. CuSn (SLID) or SnAg micro bumps at the wafer topside. This is followed by bonding a temporary carrier wafer to undergo backside processing by thinning isolation and backside wiring.

The vias are etched using the Bosch process (DRIE) with typical diameters between 1 µm and 40 µm with depths between 16 µm and >70 µm. One important factor regarding post-CMOS processing of vias from the wafer front side is to etch through all the inter-dielectric layers of the backside before etching silicon. This means the dry etch process will vary from supplier to supplier, so the etch process has to be adapted for each wafer type.

There are different approaches for metal filling of the TSVs. For small-sized vias, W CVD or Cu CVD is used for the filling. For medium-sized vias, CVD deposited seed layers followed by Cu electroplatings are used. For larger vias, the choice is sputtered seed layers followed by Cu electroplating.

The thermo-mechanical simulation and characterization of TSVs is important to identify the key processes and parameters responsible for the final stress-strain balance of TSVs. So for example, CVD copper filling compared to tungsten reduces the stress of the top and bottom of TSVs by increasing the stress in the middle of the vias. There are ongoing activities to match design, process, and reliability not only for the TSVs but also for the complete stacked configuration.

Different approaches for the interconnection of 3D assemblies include direct oxide bonding (or adhesive bonding) and direct metal bonding, which is preferred by Fraunhofer. For direct metal bonding, electroplated Cu at one device pad and electroplated copper tin (Cu-Sn) at the counterpart pad is used. The interconnect structures are brought into contact and heated up under pressure, where copper thin is transferred into diffused alloy with Cu-Sn in the inter-metallic Cu3Sn phase. This IMC has a high re-melt temperature of more than 600°C. This approach is known as solid-liquid inter-diffusion (SOLID) technology. Alternative materials for direct metal bonding are micro bumps using solder such as tin silver.

As a member of the EMC3D Consortium, Fraunhofer IZM acts as a technology consultant for complete 3D process integration and provides test design device wafers. Currently, they support processes like insulated-barrier and seed-layer deposition inside the TSVs, TSV filling using ECD, as well as backside processing and interconnect preparation and deposition for the stacking process.

3D integration technology is a main stream technology in Fraunhofer IZMs roadmap. Concepts will be used for fabrication of different 3D configurations such as stacked sensors, memories and controllers for ultra-miniaturized sensor nodes (eGrain, e Cubes), high performance controller memory buildups, and memory device stacks. The progress in system integration and semiconductor packaging will be boosted by 3D integration which is an integral part of the "More than Moore" and the "System in Package" strategy. Fraunhofer IZM provides a complete 3D Integration process flow and technology for 8" wafer using TSVs. These technologies will be characterized by adapted thermo-mechanical and electrical characterization for reliability characterization.

EV Group

The primary driver for thin-wafer processing is the real estate consumption of the vias. A device with a high-via density necessitates a very small via diameter. Otherwise, the vias would consume too much area on the microchip.

On the other hand, there are technical limits for via processing in regards to the aspect ratio it can support. For example, assume via processing technology allows for a challenging aspect ration such as 25:1. This would mean that with a 100-µm wafer, we have to deal with a via diameter of 4 µm. If a thinner wafer of 50 µm is used, then we only have to deal with a 2-µm via diameter, which offers a significant device performance advantage.

The second driver for thin-wafer processing is its cost effectiveness and cost performance. Lower via depth allows faster via drilling, as well as for via filling later on. Likewise, a reduction in via aspect ratio significantly improves via filling process throughput.

Integration Schemes for Chip Sacking with TSVs
There are a few fundamental concepts for chip stacking with TSVs. The first is face-to-back integration, which means that the backside of the first device wafer is bonded or connected to the front side of the second device wafer. The main advantage of this integration scheme is that the stacked wafer or device resembles a standard wafer or die, which means that standard processes for test, assembly, and packaging can be used.

Likewise, if additional layers on top of this wafer stack need to be added, the exact same integration processes are used for the first and second wafer in order to add a third, fourth,or additional wafers.

The competing approach would be a face-to-face integration, where the front side of the first device wafer is connected to the front side of the second device wafer. The difference here is that special processes for test, assembly and packaging are required. The resulting wafer stack does not resemble a standard wafer, which means that additional layer integration for multi-layer stacks needs different integration processes. However, a big advantage of this process flow is that it does not require thin-wafer processing.

Thin-wafer Handling
In thin-wafer processing, the very first challenge is thin-wafer handling. There are two options to address this challenge. The first is to modify the equipment to make it capable to handle thin wafers with specialized cassettes and robot end-effectors, as well as specialized process modules such as a pre-aligner and wafer chucks. These technologies currently exist in manufacturing, however, it is costly to upgrade each individual portion of the equipment, and often these technologies only accommodate wafer thicknesses in the range of approximately 75 to 100 µm and above, with no clear technology roadmap to address thinner wafers such as 50 or 25 µm.

The second and competing approach is a temporary bonding and subsequent debonding of the device wafer to a carrier wafer. The wafer is temporarily bonded face down to a carrier wafer, followed by back filling and backside processing. After final backside processing, the device wafer is released from the carrier wafer, and is unloaded either by the use of dicing tape on the thin frame or onto a coin stack.

Advantages of Temporary Bonding and Debonding
There are several advantages of the temporary bonding concept. The first is that the carrier wafer gives mechanical support protection for the thin device wafer, which uses standard wafer fab equipment for backside processing. In the case of very thin wafers, it is an enabling step for wafer-level processing overall. So, with temporary bonding and debonding, thin wafers can be processed on every piece of equipment in the fab without having to retool and without the need for special end-effectors, chucks or wafer cassettes. In fact, the same processes used for thick wafers can be used for the bonded wafer stack.

Additionally, this approach is scalable in terms of roadmaps moving to production on thinner wafers and different product designs, as well as different wafer stress levels related to a number of metallization layers, etc. So the concept of temporary bonding enables thin-wafer processing in existing fabs with existing equipment.

Process Flow for Temporary Bonding
Initiated with a coating step, either the carrier or the device wafer is coated. In a dedicated bond chamber, the temporary bonding step takes place (Figure2). EV Group has partnered with Brewer Science to develop a total solution consisting of the process, material, and equipment. Brewer Science, a specialist in polymer engineering, has developed a new high-temperature spin-on adhesive for temporary bonding called the WaferBOND HT series and WaferBOND HT 250 material. This material is a commercially available material, allowing wafers to be processed at high temperatures, in the range of 220°, for an extended period of time. Then, after backside processing, the device wafer is debonded from the carrier wafer. This material, which is a thermal plastic, allows a "slide-off" debonding mechanism. While it is fast, it is also a very soft process for thin wafers, eliminating risk of wafer breakage. Lastly, it is very easy to clean the wafers with the use of standard polar solvents.

The EVG850 temporary bonding/debonding platform and the Brewer Science WaferBOND HT series has been qualified by the EMC3D Consortium for the processing of thin wafers for TSV manufacturing.

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