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Looking to the Future, Dissecting the Past at SEMInvest
Discussions at this year's SEMInvest concerning 2002 sometimes sounded like reports on the Canadian sports scene -- would 2002's recovery be canoe-shaped, or more like a hockey stick?
Top executives gathered in New York City looked back over the downturn and ahead to the upturn, discussing what the economic drivers would be in 2002 during a panel moderated by analyst Byron Walker of UBS Warburg.
Roger Blethen, CEO of LTX Corp., noted that a variety of end uses and chip sets will lead the way in 2002, including mobile applications, the Internet, broadband advances, DSPs, and power management.
Teradyne CEO George Chamillard pointed to one major driver -- the Internet.
"There's three problems with the Internet: It's too hard to use, it's unreliable, and it's too expensive," he remarked. "These are great problems -- they're solved by silicon."
Chamillard noted that the worldwide economy is recovering on a GDP basis and that consumer confidence has stayed up, as well. The end of the year would see a very fast growth rate (like a hockey stick -- long and flat, with a sharp upturn at the end).
"Semiconductors are like drugs -- the world is hooked," Chamillard quipped.
Chamillard also noted that chipmakers will still be driven by the economy -- they'll only invest in new equipment, new capacity, when they absolutely have to.
Axcelis CEO Mary Puma agreed, adding, "There's definitely a delta out there from a customer spending standpoint. They are waiting for the time to say 'Now's the time to turn it on.'"
On the whole, however, Chamillard said he thought 2002 wouldn't be spectacular, stating, "If we have a flat '02, I won't feel blue."
A big push toward spending for advanced geometries and 300mm came a few weeks ago, commented Paul McLaughlin, CEO of Rudolph Technologies, in the form of Intel's Developer Forum. Intel announced the shift of Pentium processors from 0.18µm on 200mm wafers to 0.13µm on 300mm. That translates roughly to four times the number of die at a 30 percent lower cost, McLaughlin said.
"That's the stimulus for the rest of the industry to go down that road," McLaughlin predicted.
McLaughlin noted the key materials shift now underway, and gave the gathered investors and analysts in the audience a plug for copper.
"The business has changed. It's a materials business now, not a process business," he explained. "I think you'd be unwise to not bet on copper taking over and passing (aluminum). The economics are just too powerful."
McLaughlin also pointed to the continuing strength of the foundry model as something to be calculated into the strength of the recovery, and that foundries would spread significantly beyond Taiwan, adding that, "We're going to wake up in 24 months and see foundries all around us in a big way. The business of foundries will outpace the DRAMs in the next 18 months."
Alex Oscilowski, CFO at Kulicke & Soffa Industries, remarked that the foundries have made the fabless companies competitive, transforming the traditional business model.
Oscilowski also noted that K&S, in the backend, has already begun to enjoy the recovery.
"For our business, the upturn started," he proclaimed. "It's very real -- it started a quarter ago."
So far, Oscilowski reported, the recovery for K&S is technology-driven, with 50µm bonders leading the way. Oscilowski said K&S didn't believe the recovery was going to be "aggressive."
McLaughlin noted that Rudolph is seeing some fringe activity, with tape-outs at leading edge foundries. Puma reported some technology buying activity; quotation activity is up, technology orders are a bit up, "but not significantly."
Looking back over lessons learned in the latest downturn, Puma noted, "What we've learned from the last cycle is that we've learned nothing!"
Blethen, of LTX, commented that companies in the tool industry all look to their customers' forecasts to chart their own way, and not at economic factors. A 3 percent swing in GDP translates to a 25 percent change in product sales, which relates to a 75 percent shift in semi tool sales, said Blethen.
"We have to start paying more attention to underlying demand drivers," stressed Blethen.
McLaughlin related that he keeps a close eye on the consumer price index for business planning purposes. Earlier in its life, the tool industry was really a business-to-business market, he said. It's different now, he suggested, and smart companies follow the consumers, rather than just relying on customers' reports and forecasts.
Still, said Oscilowski, "It's also difficult to tell a customer you don't believe them, and you're just not going to fill the order."
Better forecasting isn't the key, suggested Puma -- managing the downturn is. Blethen added that the industry needed to act more aggressively in response to market changes, and needs to focus on the future, rather than the past.
"If we think too long about the last cycle, we're going to miss the one that's coming," he noted.
Chamillard said he thought the industry "is wearing a hair shirt more than it has to." While the tool industry is often beaten up for poor forecasting techniques, "what area missed it this time?," asked Chamillard.
Of course, said Oscilowski, talk of managing the cycles better and ramping smartly, with excess capacity concerns held firmly in mind, is nice in theory, but not really practical.
"It's unlikely the industry will behave better," he remarked. "We behave like pigs at the trough during the up times."
--Matt Wickenheiser, Editor
(May 9)
Last year's IPOs -- where are they now?
It seems that the semiconductor IPO well has begun to run dry, at least for the time being. It has been months since a chip-related company has filed for its initial public offering. And yet, if one looks at companies that went IPO during late 2000 into 2001, it seems that the public market has been kind to them.
Magma Design Automation, Cupertino, CA, went IPO on Nov. 19, 2001, with an initial offering of 4.85 million shares at a price of $13. Magma's software enables chip designers to reduce the time required to design and produce ICs. The company utilizes FixedTiming methodology and single data model architecture to reduce the timing-closure iterations that are required between the logic and physical processes in IC design flows.
According to Magma Chairman and CEO Rajeev Madhavan, the company's customers include 20 to 30% of vendors that run at 0.13µm.
In its latest quarterly report, Magma posted a net loss of $16 million, on sales of $13.9 million. But, Madhavan has his eyes on the future. "We have an opportunity," he said. "EDA's are going through an interesting time. [They are] about to come into our terriorty."
For Magma, going IPO had a hidden benefit. According to Madhavan, going IPO "dispelled myths" that were created by Magma's competitors. Madhavan told WaferNews that its competitors were spreading rumors that the company was going out of business. He said that Magma's IPO "created certainty" about the company's status.
Additionally, Madhavan said that being a public company "puts [forward] quantifiable numbers, which make mergers and acquisitions easier." However, he declined to comment on any future M&A's for Magma.
Timing proved to be a major benefit for another company that went IPO in 2001. Nassda Corp., Santa Clara, CA, went IPO on Dec. 12, with an initial offering of five million shares at $11 each. But, its IPO happened later than first anticipated. Nassda postponed its IPO the first time, and according to CEO and Chairman Sang Wang, the timing ended up being perfect. "When we went in December, there was a market uplift," he said. "We caught that momentum, and created a good initial success."
Nassda is a provider of full-chip circuit verification software for nanometer semiconductors. "We'd like to become a strong nanometer solution company that helps worldwide users to be able to design, verify, and optimize their large nanometer circuits," he told WaferNews.
For its first fiscal quarter of 2002, Nassda earned $1 million on $7.1 million of sales. Wang said that 17 out of the top 20 chip-related companies are users of Nassda's products. And he hopes that is just the beginning. "We just need to continuously expand our solution and product features, and to continue to support our users," Wang commented. "Eventually, the traditional digital tools will not be adequate. People need to handle big circuits and have a reasonable turn around." According to Wang, that's Nassda's niche.
ChipPAC, Fremont, CA, went IPO on Aug. 14, 2000 under different circumstances. "When we went public, we made money, and had 7,000 employees. It's different in that we were a large scale global enterprise, in contrast to a typical VC backed company," said Robert Krakauer, CFO of ChipPAC.
At its IPO, ChipPAC offered 10 million shares at $12 each.
For ChipPAC, being a public company wasn't very different than being privately held. "We run this company with a long term vision of a focused operational approach and a financial approach," Krakauer told WaferNews. "How we run on a private and public basis is the same. We now have public share holders that have joined the ranks of private shareholders."
ChipPAC is a provider of semiconductor packaging design, assembly, test, and distribution services. And according to Krakauer, ChipPAC "used to be a fast follower, but now [it's a] technology leader."
For 4Q01, the company reported a net loss of $60.1 million on sales of $76.8 million. But the numbers are not the only gage of success. "We've met or exceeded street guidance every quarter in 2001," Krakauer said.
In terms of technology, Krakauer said that the company has a broad portfolio of packaging, and it has strong market share in wafer thinning, system in a package, and die stacking. The CFO said that the company's key customers include Intel, LSI Logic, IBM, Atmel, and Fairchild, among others.
At press time, Magma was trading at $19.55, Nassda at $15.80, and ChipPAC at $7.93.
--Rachel Robinson, Associate Editor
(May 2)
An Alien Technology for Assembling ICs
Gravity, one of the most familiar forces of nature, is at the heart of Alien Technology's fluidic self-assembly (FSA) process. FSA is a technique to assemble ultra high volumes of crystalline silicon drivers into plastic substrates for displays, RF ID tags, and other portable electronic devices.
The FSA process starts with forming ICs into trapezoidal shapes (called NanoBlocks) with a 54.7° beveled cut using CMP and crystalline-plane-specific chemical etching. The ICs can range in size from 10µm to several hundred microns on a side. When suspended in an aqueous solution over receptor holes in the display, the ICs fall into place, literally. The receptor holes, which have been micro-embossed into the substrate, match the size and shape of the NanoBlock ICs and are placed with an accuracy of +/- 1µm. The company credits the use of chemical etch instead of a die cutting saw for being able to achieve a 10µm etching street vs. the typical 100µm sawing street.
The law of large numbers governs the actual results of the fall into receptor holes. Those ICs that don't make it are removed from the fluid, cleaned and re-used. A polymer coating on the surface of the aqueous solution prevents damage of the NanoBlocks. Alien, of Morgan Hill, Calif., claims a yield rate in excess of 99 percent.
Tapping the mass consumer markets means keeping costs low -- the main reason Alien decided to implement the FSA process on flexible (rather than rigid) displays, for mass production.
"The TABlike (tape automated bonding) design rules are compatible with our initial product-embedded displays for Smart Cards," explains Anne Chiang, VP of product engineering and displays. "We've chosen to use continuous roll-to-roll manufacturing to meet low cost/high volume objectives."
The production line is planned to be operational in 2003.
The company is staking its future on its ability to be able to place between two and four million ICs/hour, or more, within the next year. Company VP of Finance and CFO John Hemingway believes the company's sweet spot is in being able to assemble tens of millions and even billions of ICs for pennies -- a feat that he thinks can be accomplished in 2004.
Being able to assemble hundreds of billions of ICs for only pennies is becoming increasingly important. Kevin Ashton, executive director of the Auto ID Center at the Massachusetts Institute of Technology, has presented data showing that top-ranked consumer products companies will need more than 550 billion smart tags per year for tracking merchandise. For example, Coca-Cola has an expected need to track 200 billion units/yr in its supply chain, the US Postal Service, 205 billion, and Wal-Mart, 30 billion. The center is focused on the premise that by embedding intelligence into physical objects, consumer goods become able to communicate with each other, with businesses and with consumers.
While Alien Technology first started using FSA to package ICs for the displays used in smart cards, it believes the market for RF ID tags will be a much more potent market.
"Right now, the price per RF ID tag is high -- about $0.30 to $1.00 or even higher depending on the operating frequency and functionality," explains Chiang. "But we can get the price down to about $0.05/tag in 2004."
--Debra Volger, Technical Editor
(April 25)
A Futuristic AVS Conference
From air gaps, to ALD (atomic layer deposition) at room temperature, to CVD vs. SOD (spin-on dielectrics) and VICs (vertically integrated circuits) ? the recent AVS Conference on Microelectronics and Interfaces was a voyage into the future.
VIC, a 3-D-integration technology, is being held out as hope by Infineon Technologies' M. Engelhardt for the manufacture of ICs several generations beyond the limits of optical lithography. The idea is to use interchip vias for electrical connections in what is essentially a wafer stack -- with the top wafers being thinned and glued onto planarized bottom wafers. The technique presented by Infineon uses only CMOS-compatible processes and no wafer backside processing. Because the process uses fully processed and electrically measured/tested product wafers, overall yield may be limited by the ability to have perfect bonding of the vertical interconnects.
Another futuristic pursuit that will rely on reliable manufacturing processes is the use of either porous low-k dielectrics, or even air, coupled with Cu to minimize the RC delay of the interconnect structure (paper presented by S.V. Nitta of IBM T.J. Watson Research Center). While David Wang, president and CEO of ACM Research, thinks using air is a good idea, he hasn't seen a viable approach published that can be implemented into semiconductor devices taking into account multi-layer structure and device reliability. "However, nothing is impossible until we try it," says Wang.
Trikon Technologies' Andy Noakes, CVD products marketing manager, reports that the company is betting that CVD low-k dielectrics are the right way to go rather than SOD.
"CVD will beat SOD because it is lower cost and presents less risk," states Noakes. "The industry has used CVD for years and logic manufacturers will choose CVD over SOD every time if the results are equal."
Noakes does add that SOD is extendible down to k values of about 2.0 and maybe a bit below, so the challenge for CVD is to match these results and International SEMATECH (ISMT) is addressing the issue.
ISMT Project Engineer Jeff Lee presented results of its evaluation of Trikon's Orion CVD dielectric material, which showed the feasibility of integrating it in single level metal Cu damascene test structures. Lee reports that the material met ISMT's specifications for characterization at the one-level build and the organization will continue to test the material over a four- to six-month timetable, noting that the material needs to be optimized for etch, ash, CMP, and other processes.
Interest in ALD Grows
Judging by the number of papers on ALD -- 13 total, four more than those for the next highest categories of CMP and plasma etching -- interest in this monolayer approach is growing. While ALD at temperatures above 200°C has achieved some measure of being considered a manufacturable process, doing so at lower temperatures (possibly as low as room-temperature) is still being evaluated. The interest in room temperature ALD is spurred by the growing requirement to minimize thermal budgets (e.g., minimize diffusion of dopants), as well as fulfilling a need to explore applications such as deposition on plastics. Arthur Sherman, president of Sherman & Associates, also believes deposition of Cu seed layers could possibly benefit from a low temperature ALD process as a way to minimize agglomeration effects that occur even at moderate temperatures. Farther out in the future, he speculates that growing amorphous metals, which could be excellent barrier layers, could be accomplished using room-temperature ALD to prevent film crystallization.
Sherman, and others (IBM Research, UC Berkeley), have already been able to demonstrate room-temperature deposition of aluminum oxide, titanium and titanium nitride. Recently, ASM/Genitech reported preliminary data on low temperature tantalum.
"I think the first commercially viable low temperature ALD process will be for high-k gate oxides, because growing a 30Å film uniformly over a 300mm wafer needs an inherently very uniform process," predicts Sherman. After that, the next application the industry might pursue is barrier films. "It won't be possible to use sputtering to deposit layers into 10:1 aspect ratio holes," he explained.
--Debra Volger, Technical Editor
(April 18)
Organic FETs Emerging Out of OLED Technology
While flexible manufacturing is just a niche in overall microelectronics, Robert Pinnel, CTO for the US Display Consortium (USDC), sees the emerging field growing significantly in importance.
"The Department of Defense, for example, is increasingly inserting flat panel displays (FPDs) into platforms because over 80 percent of information from these systems is obtained visually. The growing interest in 'flexible' displays comes from the fact that high resolution active-matrix displays fabricated on flexible substrates improve durability, lessen packaging weight, and improve form factor of portable devices," says Pinnel, who spoke recently at the USDC Flexible Manufacturing Workshop held in Phoenix, AZ.
The workshop provided an interesting cross section of fabrication technologies being developed for flexible manufacturing. While early concentration on organic materials has been for organic LEDs (OLEDs), clearly the technology is now evolving to include organic FETs (OFETs).
For example, Universal Display Corp. (UDC), Ewing, N.J., is developing high-efficiency small-molecule OLEDs (also flexible OLEDs or FOLEDs) based on electro-phosphorescence rather than more conventional fluorescence. The small molecule OLEDs provide up to four times higher power efficiencies -- brighter (e.g., red at 6-25 cd/A), longer-life LEDs with lower power consumption (e.g., deep red OLEDs have a 100,000 hr life at 70 cd/m2).
FOLEDs provide unique and exciting opportunities for applications such as UDC's pen-like Internet communication device. UDC's Mike Hack also showed recent UDC results with a video-rate plastic phosphorescent OLED display -- a 240 x 64 passive matrix display with 80 dpi resolution, 120 Hz refresh rate, 32 gray levels, fabricated on 0.175mm low-cost polyethylene terephthalate (PET).
Reflective Optics
E Ink Corp. (Cambridge, Mass.) has a technology, using materials found in inks and paper, that creates contrast by printing fluid-filled microcapsules with positively charged white pigment chips and negatively charged black pigment chips. This technology, developed in partnership with Toppan Printing, achieves paper-like Lambertian reflective optics that are insensitive to the position of illumination source (a common problem with reflective LCD based displays).
Peter Kazlas of E Ink says, "Electronic ink combined with am amorphous-silicon TFT backplane on foil provides a viable pathway to high-resolution, low cost flexible paper-like displays -- technology for smartcards, cell phones, PDAs, peripheral displays, electronic books and newspapers, wearable displays, large area displays."
Late in 2001, E Ink opened a fab in Woburn, Mass., for commercializing this technology.
According to Rag Apte from Xerox PARC (Palo Alto, Calif.), "Present manufacturing is too expensive for ubiquitous displays, medical imaging, smart cards, ID tags, etc."
Using ink jet printing techniques, PARC engineers have demonstrated about 20µm minimum features (determined by drop size) and layer registration on discrete and self-aligned TFTs in a matrix addressing structure.
Combined with these basic technologies, some companies are pursuing roll-to-roll fabrication methods. Robert Priano from Vitex Systems (San Jose, Calif.) noted that for the needed growth in the flexible OLED display market, cost advantages are as important as technical innovations.
"We need to look closely at the cost advantages available with roll-to-roll manufacturing," he explained.
Along with the continued evolution required in materials, Priano sees the need for processes including roll-to-roll patterning and extreme cleanliness. There are also some integration issues that need to be solved, including vacuum-to-atmosphere integration and process speed matching.
Breaking Out
Participants in one of the workshop's breakout sessions tagged "dynamic advertising" as an ideal applications opportunity to develop roll-to-roll processing for large-area, low-power displays. Participants concluded that the weight advantage gained through the use of OLED or electrophoretic technologies on plastic substrates should be compelling. The serious conflict between good color gamut and wide-angle viewing that is faced by manufacturers of reflective LCDs provides a clear opening for alternative technologies.
Another intriguing side of the application of organic materials in microelectronics fabrication is OFETs.
The OFET debate is that while the common wisdom has been that the technology is not good enough yet, according to Tom McLean, director of business development at Aveica Electronic Materials (Manchester, UK), "the acceptance attitude is changing to 'it is good enough.'
"While OFETs still need to be delivered in practice, today the view is that the relatively low carrier mobility of OFETS (i.e., 10-1 cm2/Vs) compared to silicon-based technology is potentially good for non-high performance applications where OFETs are seen as 'solutions' for larger area, low cost/unit area, flexible substrate, and short runs (up to 2000) applications."
McLean noted that Aveica has made progress with ambient stable processing from solution coating processes without precursors to achieve p-type FET materials where the target in 2002 is >10 to 2 cm2/Vs mobility. Aveica engineers are also working on n-type, dielectric, and conductors materials. Perhaps the most difficult issue with dielectrics is preventing the solvent base, potential cross linking, and kinetics from damaging the layer it is deposited to.
But clearly, transistors are emerging out of OLED technology.
At the conference, Stuart Evans of Plastic Logic (Cambridge, UK) showed his company's work in demonstrating PLL IJ-TFTs on flexible substrates that achieved an 10-2 cm2/Vs mobility.
The Plastic Logic fabrication process is all additive to a modified flexible substrate using ink jet printing for the source, drain and gate, and spin coating for the semiconductor and dielectric layers. Company engineers have a developed process for channel lengths of 5- to 10µm and have demonstrated experimental lengths of 1µm. The Plastic Logic printing process for active polymer electronics is inherently scaleable in substrate size and economic batch size.
-- Pete Burggraaf, Technical Editor
(April 11)
Government Urged to Fund University Research
Semiconductor technology is a key driver for not only the U.S. economy, but for the world's, as well, but the future of the industry may be in peril if the U.S. government doesn't step up to the financial plate, according to the Semiconductor Industry Association.
If the U.S. is going to keep on pace in terms of technological growth, the federal government has to provide additional funding for university research for the physical sciences and engineering, the SIA believes.
According to the SIA, from 1993 to 1998, federal funding for key disciplines declined considerably. Funding for math and physics research declined some 20 percent during that time, funding for chemistry dropped about 10 percent, and funding for some fields of engineering dropped between 20 to 40 percent.
The danger here, Juri Matisoo, VP of technology at the SIA told WaferNews, is that with a decrease in funding comes a decrease in professors and students. That decrease leads to a smaller pool of qualified professionals, which, in turn, translates into a lack of the university-based research which is often the basis for the future of information technology.
Technical Challenges
Staying in line with Moore's Law had led to faster U.S. economic growth, greater productivity, higher federal budget surpluses, and the creation of higher-paying high-tech jobs. But, as technology advances and new technical challenges emerge, SIA insists that current levels of government funding are not adequate.
The group believes that within the next six years, the semiconductor industry will be facing technical challenges for which there are no known solutions. With that knowledge comes the conviction that federal funding for research is imperative.
"I don't think that the funding has ever been sufficient," Matisoo said. "SIA has really put its efforts behind getting Congress to increase funding for universities. If you look at federal funding, the budgets for institutes of health have gone up. On the other hand, the physical sciences have been left behind, with budgets decreasing over five or more years."
Matisoo told WaferNews that the Clinton administration increased the National Science Foundation (NSF) budget by 10 percent during his last two years in office. During the first year of the Bush administration, an increase of only 1 percent was proposed, but, after time spent lobbying Congress, it went up by 7.5 percent.
"Is the 7.5 percent increase enough?" Matisoo asked. "I doubt it."
With the physical limits of semiconductor performance approaching, the latter stages of the ITRS roadmap would be affected by the lack of funding to university research. "That's where the revolutionary ideas come from," Matisoo said.
According to the SIA, a loss of international leadership in semiconductor technology would be economically damaging, and would hurt the ability of the US to provide for national security. With that in mind, SIA believes that with cooperation between the US government and the chip industry, it can be ensured that the basic physical science and engineering needed to drive progress, and the economy, will be in place.
SIA supports the following initiatives:
** Multiyear funding for university-based research in advanced microelectronics by the defense department;
** A tripling of the funding for physical sciences of chemistry, materials sciences, physics, mathematics, electrical and communications systems engineering, computer and information science and engineering programs, and related engineering research centers;
** $5 million for work at NIST for measurement technology at the nanometer level.
Additionally, a top priority for SIA is multiyear funding for the Office of the Secretary of Defense's Government-Industry Co-sponsorship of University Research (GICUR) program, which it hopes will receive $9.2 billion in FY02, up from FY01's $6.7 billion. Currently, four semiconductor-related centers are under the GICUR program, with activities at 22 universities nationwide. The centers are the Gigascale Silicon Research Center/Design and Test at UC-Berkeley; the Interconnect Focus Center at Georgia Institute of Technology; the Materials, Structures and Devices Focus Center at MIT; and the Circuits, Systems, and Software Focus Center at Carnegie Mellon University.
According to SIA, the funding will allow MIT and Carnegie Mellon to reach planned levels and experience growth in their programs.
SIA also recommends that the Future Years Defense Program include sufficient funds to allow the focus center program to grow as originally planned in 1999 ? the budget calls for: 2002 - $10 million; 2003 - $13 million; and $15 million in 2004, 2005, and 2006.
The long-term increase in the Future Years Defense Program should be within the context of the larger increases in defense R&D, according to the SIA. In FY02, the Department of Defense will receive some $49.2 billion in funding, with a proposed increase to $54.5 billion in FY03.
SIA also supports the National Nanotechnology Initiative, and believes that funding should be increased from the FY01 level of $446 million to $579 million in FY02, and $679 million in FY03. According to published reports, President Bush's budget, which has been sent to Congress, requests 17 percent more, or $679 million, for the federal Nat. Nanotechnology Initiative.
The group also supports a doubling of the budget for the NSF from FY01 $4.4 billion to $8.8 billion in FY06.
--Rachel Robinson, Associate Editor
(April 4)
US MEMS Industry is Growing Rapidly, Says MIG
"We are on our way" seems to be the sentiment coming from the MEMS Industry Group (MIG), which recently reported that the US MEMS industry will grow from 2000's $2 to $5 billion to an $8 to $15 billion industry by 2004.
"MEMS may not yet be a household name," said John Seely Brown, chief scientist as Xerox, and MIG founding co-director. "But with the continued rapid adoption of MEMS technologies into products and devices of virtually every nature, it's just a matter of time before MEMS is as much a part of the common understanding of technology as the microchip is today."
According to a recent report issued by MIG (Pittsburgh, Pa.), there are approximately 1.6 MEMS devices per person today in the US. By 2004, MIG expects that number to grow to nearly five per person ? a compound annual growth rate of 45 percent.
According to Ken Gabriel, MIG founding co-director and professor of electrical and computer engineering at the Robotics Institute at Carnegie Mellon University, the report put out by MIG is the first comprehensive review of economic and other indicators about the MEMS industry. "One of the things that is significant about the report is that there is a report at all," he said. "This is the first report where the industry has come together, big and little companies, and has worked in context of the MIG over the last 10 months, to put together a consensus view of what the drivers are and what the challenges are."
Growth in Numbers
The study also found that more than 40 percent of US-based MEMS companies were founded between 1995 and 2001, with an average of 10 new companies per year founded over the past three years. To Vladimir Vaganov, founder and CEO of MegaSense (Sunnyvale, Calif.), a provider of integrated photonic micro-modules and micro-subsystems, the rapid growth proved to be both a blessing and a curse.
"Lately, a lot of MEMS companies started up and the majority of them didn't have any experience in MEMS manufacturing. Because of that, they shook things up a bit, and hurt a good reliable reputation."
He emphasized, however, that MEMS themselves are reliable and have a solid future.
"The industry is still maturing," he said. "It'll take time before we reach the level of the IC industry."
According to MIG, employment growth in the US MEMS industry has "exploded." It found that the level of employment in 2001 was 30 times greater than in 1985.
Gabriel told WaferNews that the MEMS industry is getting highly trained graduates wanting to enter its work force. He said that students are being educated via federal funding for MEMS research, and research projects from universities.
In reference to the positive findings of the MIG study, Gabriel commented that the MEMS industry has been built on existing semiconductor infrastructure, which is a real benefit. "90 percent of what's used in processing equipment for the semiconductor industry can be used for MEMS," he said, adding that there are some differences and additional needs for MEMS that go beyond the chip industry. He pointed to infrastructure for optical MEMS devices, which are going to be different than that of the infrastructure for advanced biomedical applications as examples of diverse needs in the same general sector.
Vaganov said that the goal of MEMS was to create a complete system that will see, smell, hear, and process information, and then react to it.
Gabriel agreed, adding that MEMS is giving computing chips that can't sense anything the eyes and ears to perceive and act upon the physical world.
Vaganov, like MIG, is very optimistic about what lies ahead for MEMS. "Any field, and any area of our lives will be affected by MEMS sooner or later," he told . "It is enormous, with uncountable applications."
--Rachel Robinson, Associate Editor
(March 28)
Value Moves to Materials
Materials Market Could Surpass Equipment in 2002
If the analysts are anywhere close to right, chipmakers may spend more on materials than on equipment this year, for what may be the first time ever.
Materials sales held up better than equipment last year, as they always do in a downturn, when chipmakers stop investing in new fabs. But sales of materials also held up better than those of the chips themselves, as chipmakers continued to buy increasingly sophisticated (and increasingly expensive) materials technologies to get those finer geometries.
So while Dataquest estimates that tool sales plunged 37 percent and semiconductors dropped 30 percent in 2001, SEMI says total semiconductor materials sales declined only 20 percent, to $21 billion, edging up on the $25 billion tool market. The trade group expects materials sales to increase 11 percent in 2002, slightly outpacing an 8 percent or so increase in silicon area consumption, to reach some $23.4 billion. That's as big or bigger than the $20 to $24 billion forecast for the semiconductor equipment market, where VLSI Research expects a 5 percent decline, Dataquest another 20 percent.
"Even during a downturn, chipmakers are transitioning to things like more advanced resists," explains Dan Tracy, SEMI senior market analyst for industry research and statistics.
The most significant contributor to materials market growth is a projected 17 percent jump in the roughly $2 billion gas sector this year, thanks to strong demand for specialty gases like NF3. The semiconductor gas business even avoided any decline in sales through 2001's plunge.
"Even if the fab is idle, they still need to keep gas flowing through the tools," points out Tracy.
Also expected to expand at a 17 percent clip: Photoresist ancillaries, driven by the increasing need for antireflective coatings at smaller geometries. On the packaging materials side, the growth sector is plastic substrates, where SEMI projects a 22 percent increase. And those pricey 300 mm wafers aren't showing up in the figures yet, as less than 5 percent of wafer shipments so far are 300 mm, mostly still for testing.
Tracy also forecasts strong 33 percent growth for new materials like CMP slurries, low-k dielectrics, and copper plating solutions, though the small base means sales of all these hot products combined will still come to only $450 million in 2002.
But while these various advanced materials are boosting total materials sales, those sales are divided among a crowd of competitors in most sectors, leaving relatively small revenues to cover staggering development costs. Capital costs through early production of 157nm resist, for example, will be nearly $33 million for each supplier, figures Micron Technology's Photo Lithography Section Manager J.J. Johnson. That means a supplier with 15 percent of the total $660 million resist market would have to spend 33 percent of a year's total revenues to develop this one product.
"This capital cost problem holds true for them all," says Tracy. "The huge capital costs for development will force consolidation looking ahead."
--Paula Doe, Contributing Editor
(March 21)WaferNews is published weekly by PennWell. To request a free sample issue or to receive subscription information, please forward requests to Christine Tourgee, WaferNews, 98 Spit Brook Rd., Nashua, NH 03062; Tel: 603-891-9174; Fax: 603-891-0574.
A Futuristic AVS ConferenceFrom air gaps, to ALD (atomic layer deposition) at room temperature, to CVD vs. SOD (spin-on dielectrics) and VICs (vertically integrated circuits) ? the recent AVS Conference on Microelectronics and Interfaces was a voyage into the future.
VIC, a 3-D-integration technology, is being held out as hope by Infineon Technologies' M. Engelhardt for the manufacture of ICs several generations beyond the limits of optical lithography. The idea is to use interchip vias for electrical connections in what is essentially a wafer stack -- with the top wafers being thinned and glued onto planarized bottom wafers. The technique presented by Infineon uses only CMOS-compatible processes and no wafer backside processing. Because the process uses fully processed and electrically measured/tested product wafers, overall yield may be limited by the ability to have perfect bonding of the vertical interconnects.
Another futuristic pursuit that will rely on reliable manufacturing processes is the use of either porous low-k dielectrics, or even air, coupled with Cu to minimize the RC delay of the interconnect structure (paper presented by S.V. Nitta of IBM T.J. Watson Research Center). While David Wang, president and CEO of ACM Research, thinks using air is a good idea, he hasn't seen a viable approach published that can be implemented into semiconductor devices taking into account multi-layer structure and device reliability. "However, nothing is impossible until we try it," says Wang.
Trikon Technologies' Andy Noakes, CVD products marketing manager, reports that the company is betting that CVD low-k dielectrics are the right way to go rather than SOD.
"CVD will beat SOD because it is lower cost and presents less risk," states Noakes. "The industry has used CVD for years and logic manufacturers will choose CVD over SOD every time if the results are equal."
Noakes does add that SOD is extendible down to k values of about 2.0 and maybe a bit below, so the challenge for CVD is to match these results and International SEMATECH (ISMT) is addressing the issue.
ISMT Project Engineer Jeff Lee presented results of its evaluation of Trikon's Orion CVD dielectric material, which showed the feasibility of integrating it in single level metal Cu damascene test structures. Lee reports that the material met ISMT's specifications for characterization at the one-level build and the organization will continue to test the material over a four- to six-month timetable, noting that the material needs to be optimized for etch, ash, CMP, and other processes.
Interest in ALD Grows
Judging by the number of papers on ALD -- 13 total, four more than those for the next highest categories of CMP and plasma etching -- interest in this monolayer approach is growing. While ALD at temperatures above 200°C has achieved some measure of being considered a manufacturable process, doing so at lower temperatures (possibly as low as room-temperature) is still being evaluated. The interest in room temperature ALD is spurred by the growing requirement to minimize thermal budgets (e.g., minimize diffusion of dopants), as well as fulfilling a need to explore applications such as deposition on plastics. Arthur Sherman, president of Sherman & Associates, also believes deposition of Cu seed layers could possibly benefit from a low temperature ALD process as a way to minimize agglomeration effects that occur even at moderate temperatures. Farther out in the future, he speculates that growing amorphous metals, which could be excellent barrier layers, could be accomplished using room-temperature ALD to prevent film crystallization.
Sherman, and others (IBM Research, UC Berkeley), have already been able to demonstrate room-temperature deposition of aluminum oxide, titanium and titanium nitride. Recently, ASM/Genitech reported preliminary data on low temperature tantalum.
"I think the first commercially viable low temperature ALD process will be for high-k gate oxides, because growing a 30Å film uniformly over a 300mm wafer needs an inherently very uniform process," predicts Sherman. After that, the next application the industry might pursue is barrier films. "It won't be possible to use sputtering to deposit layers into 10:1 aspect ratio holes," he explained.
--Debra Volger, Technical Editor
(April 18)
Organic FETs Emerging Out of OLED Technology
While flexible manufacturing is just a niche in overall microelectronics, Robert Pinnel, CTO for the US Display Consortium (USDC), sees the emerging field growing significantly in importance.
"The Department of Defense, for example, is increasingly inserting flat panel displays (FPDs) into platforms because over 80 percent of information from these systems is obtained visually. The growing interest in 'flexible' displays comes from the fact that high resolution active-matrix displays fabricated on flexible substrates improve durability, lessen packaging weight, and improve form factor of portable devices," says Pinnel, who spoke recently at the USDC Flexible Manufacturing Workshop held in Phoenix, AZ.
The workshop provided an interesting cross section of fabrication technologies being developed for flexible manufacturing. While early concentration on organic materials has been for organic LEDs (OLEDs), clearly the technology is now evolving to include organic FETs (OFETs).
For example, Universal Display Corp. (UDC), Ewing, N.J., is developing high-efficiency small-molecule OLEDs (also flexible OLEDs or FOLEDs) based on electro-phosphorescence rather than more conventional fluorescence. The small molecule OLEDs provide up to four times higher power efficiencies -- brighter (e.g., red at 6-25 cd/A), longer-life LEDs with lower power consumption (e.g., deep red OLEDs have a 100,000 hr life at 70 cd/m2).
FOLEDs provide unique and exciting opportunities for applications such as UDC's pen-like Internet communication device. UDC's Mike Hack also showed recent UDC results with a video-rate plastic phosphorescent OLED display -- a 240 x 64 passive matrix display with 80 dpi resolution, 120 Hz refresh rate, 32 gray levels, fabricated on 0.175mm low-cost polyethylene terephthalate (PET).
Reflective Optics
E Ink Corp. (Cambridge, Mass.) has a technology, using materials found in inks and paper, that creates contrast by printing fluid-filled microcapsules with positively charged white pigment chips and negatively charged black pigment chips. This technology, developed in partnership with Toppan Printing, achieves paper-like Lambertian reflective optics that are insensitive to the position of illumination source (a common problem with reflective LCD based displays).
Peter Kazlas of E Ink says, "Electronic ink combined with am amorphous-silicon TFT backplane on foil provides a viable pathway to high-resolution, low cost flexible paper-like displays -- technology for smartcards, cell phones, PDAs, peripheral displays, electronic books and newspapers, wearable displays, large area displays."
Late in 2001, E Ink opened a fab in Woburn, Mass., for commercializing this technology.
According to Rag Apte from Xerox PARC (Palo Alto, Calif.), "Present manufacturing is too expensive for ubiquitous displays, medical imaging, smart cards, ID tags, etc."
Using ink jet printing techniques, PARC engineers have demonstrated about 20µm minimum features (determined by drop size) and layer registration on discrete and self-aligned TFTs in a matrix addressing structure.
Combined with these basic technologies, some companies are pursuing roll-to-roll fabrication methods. Robert Priano from Vitex Systems (San Jose, Calif.) noted that for the needed growth in the flexible OLED display market, cost advantages are as important as technical innovations.
"We need to look closely at the cost advantages available with roll-to-roll manufacturing," he explained.
Along with the continued evolution required in materials, Priano sees the need for processes including roll-to-roll patterning and extreme cleanliness. There are also some integration issues that need to be solved, including vacuum-to-atmosphere integration and process speed matching.
Breaking Out
Participants in one of the workshop's breakout sessions tagged "dynamic advertising" as an ideal applications opportunity to develop roll-to-roll processing for large-area, low-power displays. Participants concluded that the weight advantage gained through the use of OLED or electrophoretic technologies on plastic substrates should be compelling. The serious conflict between good color gamut and wide-angle viewing that is faced by manufacturers of reflective LCDs provides a clear opening for alternative technologies.
Another intriguing side of the application of organic materials in microelectronics fabrication is OFETs.
The OFET debate is that while the common wisdom has been that the technology is not good enough yet, according to Tom McLean, director of business development at Aveica Electronic Materials (Manchester, UK), "the acceptance attitude is changing to 'it is good enough.'
"While OFETs still need to be delivered in practice, today the view is that the relatively low carrier mobility of OFETS (i.e., 10-1 cm2/Vs) compared to silicon-based technology is potentially good for non-high performance applications where OFETs are seen as 'solutions' for larger area, low cost/unit area, flexible substrate, and short runs (up to 2000) applications."
McLean noted that Aveica has made progress with ambient stable processing from solution coating processes without precursors to achieve p-type FET materials where the target in 2002 is >10 to 2 cm2/Vs mobility. Aveica engineers are also working on n-type, dielectric, and conductors materials. Perhaps the most difficult issue with dielectrics is preventing the solvent base, potential cross linking, and kinetics from damaging the layer it is deposited to.
But clearly, transistors are emerging out of OLED technology.
At the conference, Stuart Evans of Plastic Logic (Cambridge, UK) showed his company's work in demonstrating PLL IJ-TFTs on flexible substrates that achieved an 10-2 cm2/Vs mobility.
The Plastic Logic fabrication process is all additive to a modified flexible substrate using ink jet printing for the source, drain and gate, and spin coating for the semiconductor and dielectric layers. Company engineers have a developed process for channel lengths of 5- to 10µm and have demonstrated experimental lengths of 1µm. The Plastic Logic printing process for active polymer electronics is inherently scaleable in substrate size and economic batch size.
-- Pete Burggraaf, Technical Editor
(April 11)
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